In some cases of semiconductor devices having ferroelectric random accessory elements, from the viewpoint of improving in-plane uniformity of etching for forming a layered structure of ferroelectric capacitors, dummy capacitors are arranged in the peripheral circuit region so as to increase an apparent occupancy of the ferroelectric capacitors in a chip.
Patent Document 1: Japanese Laid-open Patent Publication No. 2001-196372
Patent Document 2: Japanese Laid-open Patent Publication No. 2003-100910
Patent Document 3: Japanese Laid-open Patent Publication No. 2004-095577
However, the dummy capacitors provided in the peripheral circuit region have sometimes caused pattern defect, to thereby degrade yield and reliability of the semiconductor devices.